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? semiconductor components industries, llc, 2013 july, 2013 ? rev. 3 1 publication order number: NCV7240/d NCV7240 octal low-side relay driver the NCV7240 is an automotive eight channel low ? side driver providing drive capability up to 600 ma per channel. output control is via a spi port and offers convenient reporting of faults for open load (or short to ground), over load, and over temperature conditions. additionally, parallel control of the outputs is addressable (in pairs) via the inx pins. a dedicated limp ? home mode pin (lhi) enables out1 ? out4 while disabling out5 ? out8. each output driver is protected for over load current and includes an output clamp for inductive loads. the NCV7240 is available in a ssop ? 24 fused lead package. features ? 8 channels ? 600 ma low ? side drivers ? r ds(on) 1.5 (typ), 3 (max) ? 16 ? bit spi control ? frame error detection (8 ? bit) ? daisy chain capable ? parallel input pins for pwm operation ? power up without open circuit detection active (for led applications) ? low quiescent current in sleep and standby modes ? limp home functionality ? 3.3 v and 5 v compatible digital input supply range ? fault reporting ? open load detection (selectable) ? over load ? over temperature ? power ? on reset (vdd, vdda) ? ssop ? 24 package (internally fused leads) ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable ? these are pb ? free devices applications ? automotive body control unit ? automotive engine control unit ? relay drive ? led drive ? stepper motor driver ssop ? 24 case 565al marking diagram http://onsemi.com NCV7240 awlyywwg a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 25 of this data sheet. ordering information
NCV7240 http://onsemi.com 2 out8 gnd csb sclk si en so out7 out6 out5 in1 out8 spi out1 out2 out3 out4 out5 out6 out7 in2 in3 in4 lhi vdd out1 ? out4 out4 out3 out2 out1 out1 & 5 out2 & 5 out3 & 7 out4 & 8 vdda bias, supply monitoring & por figure 1. basic block diagram on
NCV7240 http://onsemi.com 3 figure 2. application diagram (relay loads) 0.1uf 5v microprocessor so csb sclk si vdda in1 14v vbat 10uf NCV7240 gnd gnd gnd gnd out1 out2 out3 out4 out5 out6 out7 out8 en in2 in3 in4 lhi vdd 0.1uf 3.3v or 5v limp home control circuit gnd gnd out1 out2 out3 out4 out5 out6 out7 out8 gnd gnd vdda csb si en sclk so lhi in1 in2 in3 in4 vdd 1 figure 3. pinout
NCV7240 http://onsemi.com 4 package pin description ssop ? 24 symbol description 1 gnd ground. 2 gnd ground. 3 out1 channel 1 low ? side drive output. requires an external pull ? up device for operation. 4 out2 channel 2 low ? side drive output. requires an external pull ? up device for operation. 5 out3 channel 3 low ? side drive output. requires an external pull ? up device for operation. 6 out4 channel 4 low ? side drive output. requires an external pull ? up device for operation. 7 out5 channel 5 low ? side drive output. requires an external pull ? up device for operation. 8 out6 channel 6 low ? side drive output. requires an external pull ? up device for operation. 9 out7 channel 7 low ? side drive output. requires an external pull ? up device for operation. 10 out8 channel 8 low ? side drive output. requires an external pull ? up device for operation. 11 gnd ground. 12 gnd ground. 13 vdd digital power supply for so output (3.3 v or 5 v). 14 in4 parallel control of out4 and out8 ground if not used for best emi performance. alternatively keep open and internal pull ? down will hold the input low. (120 k pull down resistor). 15 in3 parallel control of out3 and out7 ground if not used for best emi performance. alternatively keep open and internal pull ? down will hold the input low. (120 k pull down resistor). 16 in2 parallel control of out2 and out6. ground if not used for best emi performance. alternatively keep open and internal pull ? down will hold the input low. (120 k pull down resistor). 17 in1 parallel control of out1 and out5. ground if not used for best emi performance. alternatively keep open and internal pull ? down will hold the input low. (120 k pull down resistor). 18 lhi limp home input. active high. a high on this pin powers up the device and activates the respective output drive inx designator while disabling outputs out5 ? out8. input spi commands are ignored, but the output register reports faults. (read capability only. no write capability.) all registers are reset coming out of lhi mode. ground if not used for best emi performance. alternatively keep open and internal pull ? down resistor (120 k ) will hold the input low. 19 so spi serial data output. output high voltage level referenced to pin vdd. 20 sclk spi clock (120 k pull down resistor). 21 en global enable (active high). (120 k pull down resistor). 22 si spi serial data input (120 k pull down resistor). 23 csb spi chip select ?bar? (120 k pull up resistor to vdd). 24 vdda analog power supply input voltage (5 v).
NCV7240 http://onsemi.com 5 maximum ratings parameter min max unit supply input voltage (vdda, vdd) dc ? 0.3 5.5 v digital i/o pin voltage (en, lhi, inx, csb, sclk, si) (so) ? 0.3 ? 0.3 5.5 v dd + 0.3 v high voltage pins (outx) dc peak transient ? 0.3 36 44 (note 1) v output current (outx) ? 1 1.3 a clamping energy maximum (single pulse) repetitive (multiple pulse) (note 2) ? ? 75 ? m j operating junction temperature range ? 40 150 c storage temperature range ? 55 150 c esd capability, human body model (100 pf, 1.5 k ) (outx pins) human body model (100 pf, 1.5 k ) (all other pins) ? 4000 ? 2000 4000 2000 v esd capability machine model (200 pf) ? 200 200 v aecq10x ? 12 ? reva short circuit reliability characterization grade a ? package moisture sensitivity level msl2 ? lead temperature soldering: smd style only, reflow (note 3) pb ? free part 60 ? 150 sec above 217 c, 40 sec max at peak 265 peak c package thermal resistance (per jesd51) ssop ? 24 junction ? to ? ambient (1s0p + 600 mm 2 cu) (note 4) junction ? to ? ambient (2s2p) (notes 4 and 5) junction ? to ? pin (pins 1, 2, 11, 12) (note 6) 68 62 30 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. internally limited. specification applies to unpowered and powered modes. (0 v to vdda, 0 v to vdd) 2. testing particulars, 2m pulses, v bat = 15 v, 63 , 390 mh, t a = 25 c. (see figure 4) 3. for additional information, see or download on semiconductor?s soldering and mounting techniques reference manual, solderrm/d and application note and8083/d. 4. 76 mm x 76 mm x 1.5 mm fr4 pcb with additional heat spreading copper (2 oz) of 600 mm 2 , ls1 to ls8 dissipating 100 mw each. no vias. 5. include 2 inner 1 oz copper layers. no vias. 6. one output dissipating 100 mw. figure 4. repetitive clamping energy test
NCV7240 http://onsemi.com 6 electrical characteristics (3.0 v < vdd < vdda, 4.5 v < vdda (note 7) < 5.5 v, ? 40 c t j 150 c, en = vdd, lhi = 0 v unless otherwise specified). characteristic conditions min typ max unit general operating current (vdda) on mode (all channels on) ? 3 5 ma quiescent current (vdda) global standby mode (all channels off) si = sclk = 0 v, csb = vdd t j = 25 c t j = 85 c t j = 150 c ? ? ? 32 35 40 a quiescent current (vdda) low iq mode si = sclk = en = 0 v, csb = vdd t j = 25 c t j = 85 c t j = 150 c ? ? ? ? ? ? 10 10 20 a operating current (vdd) on mode (all channels on) en=high, sclk = inx = 0 v, csb = vdd = vdda ? 0.3 0.5 ma quiescent current (vdd) global standby mode (all channels off) csb = vdd = vdda, f sclk = 0 hz t j = 25 c t j = 85 c t j = 150 c ? ? ? ? ? ? 20 20 40 a quiescent current (vdd) low iq mode en = 0 v t j = 25 c t j = 85 c t j = 150 c ? ? ? ? ? ? 5 5 20 a power ? on reset threshold (vdda) vdda rising ? 3.8 4.5 v power ? on reset hysteresis (vdda) 150 200 350 mv power ? on reset threshold (vdd) vdd rising ? 2.4 2.7 v power ? on reset hysteresis (vdd) 75 100 240 mv thermal shutdown (note 8) not ate tested. 150 175 200 c thermal hysteresis not ate tested. 10 25 ? c output driver output transistor r ds(on) ioutx = 180 ma ? 1.5 3.0 overload detection current 0.6 0.95 1.3 a output leakage outx = 13.5 v, 25 c outx = 13.5 v outx = 36 v ? ? ? ? ? ? 1 5 10 a output clamp voltage vdd = 0 v to 5.5 v vdda = 0 v to 5.5 v ioutx = 50 ma 36 40 44 v output body diode voltage ioutx = ? 180ma ? ? 1.5 v open load detection threshold voltage (vol) 1.0 1.75 2.5 v open load diagnostic sink current (iol) 1 v < outx < 13.5 v, output disabled 20 60 100 a output timing specifications enable (en) wake ? up time csb = 0 v en going high 80% to so active ? ? 200 s enable (en) and lhi (note 9) signal duration 50 ? ? s 7. reduced performance down to 4 v provided vdda power ? on reset threshold has not been breached. 8. each output driver is protected by its? own individual thermal sensor. 9. input signals h l h greater than 50usec are guaranteed to be detected.
NCV7240 http://onsemi.com 7 electrical characteristics (3.0 v < vdd < vdda, 4.5 v < vdda (note 7) < 5.5 v, ? 40 c t j 150 c, en = vdd, lhi = 0 v unless otherwise specified). characteristic unit max typ min conditions output timing specifications serial control output turn ? on time all channels csb going high 80% to outx going low 20% v bat ,v bat = 13.5 v, i ds = 180 ma resistive load ? 30 50 s serial control output turn ? off time all channels csb going high 80% to outx going high 80% v bat , v bat = 13.5 v, i ds = 180 ma resistive load ? 30 50 s parallel control output turn ? on time all channels inx going high 80% to outx going low 20% v bat , v bat = 13.5 v, i ds = 180 ma resistive load ? 30 50 s parallel control output turn ? off time all channels inx going low 20% to outx going high 80% v bat , v bat = 13.5 v, i ds = 180 ma resistive load ? 30 50 s over load shut ? down delay time 3 15 50 s open load detection time 30 115 200 s digital interface characteristics input characteristics digital input threshold (csb, si, sclk, lhi, en,inx) 0.8 1.4 2.0 v digital input hysteresis (csb, si, sclk, inx) 50 175 300 mv digital input hysteresis (lhi, en) 150 400 800 mv input pulldown resistance (si, sclk, lhi, en,inx) inx = si = sclk = lhi = en = vdd 50 120 190 k input pullup resistance (csb) csb = 0 v 50 120 190 k csb leakage to vdd csb = 5 v, vdd = 0 v ? ? 100 ua csb leakage to vdda csb = 5 v, vdda = 0 v ? ? 100 ua output characteristics so ? output high i(out) = ? 1.5 ma v dd ? 0.4 ? ? v so ? output low i(out) = 2.0 ma ? ? 0.6 v so tri ? state leakage csb = vdd ? 3 0 3 a spi timing (all timing specifications measured at 20% and 80% voltage levels) sclk frequency ? ? 5 mhz sclk clock period 200 ? ? ns sclk high time figure 5, #1 85 ? ? ns sclk low time figure 5, #2 85 ? ? ns si setup time figure 5, #11 50 ? ? ns si hold time figure 5, #12 50 ? ? ns csb setup time figure 5, #5, 6 100 ? ? ns csb high time figure 5, #7 1.5 ? ? s sclk setup time figure 5, #3, 4 85 ? ? ns so output enable time (csb falling to so valid) figure 5, #8, c load = 50 pf not ate tested ? ? 200 ns so output disable time (csb rising to so tri ? state) figure 5, #9 not ate tested ? ? 200 ns so output data valid time with capacitive load figure 5, #10, c load = 50 pf not ate tested ? ? 100 ns
NCV7240 http://onsemi.com 8 csb sclk 1 2 csb so so sclk si 5 6 7 8 9 10 11 12 figure 5. detailed spi timing (measured at 20% and 80% voltage levels) 4 3
NCV7240 http://onsemi.com 9 typical performance graphs figure 6. vdd low i q current vs. temperature figure 7. vdda low i q quiescent current vs. vdda 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ? 40 ? 20 0 20 40 60 80 100 120 140 temperature ( c) vdd low i q current ( a) v dd = 5 v vdda (v) 3 3.5 4 4.5 5 5.5 6.0 5.0 4.0 3.0 2.0 1.0 0 vdda low i q current ( a) 150 c ? 40 c ? 40 c figure 8. vdda low i q current vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 temperature ( c) 4.5 vdda low i q current ( a) 4 3.5 3 2.5 2 1.5 1 0.5 0 v dd = 5 v figure 9. vdd low i q current vs. vdd vdd (v) 3 3.5 4 4.5 5 5.5 1.2 vdd low i q current ( a) 150 c ? 40 c 25 c 25 c output current (ma) output voltage (v) 50 70 90 110 130 150 170 44 43 42 41 40 39 38 37 36 clamp voltage (v) temperature ( c) 180 ma 50 ma figure 10. output clamp voltage vs. current figure 11. output clamp voltage vs. temperature 1.0 0.8 0.6 0.4 0.2 0 44 43 42 41 40 39 38 37 36 ? 40 ? 20 0 20 40 60 80 100 120 140 1.4
NCV7240 http://onsemi.com 10 typical performance graphs figure 12. output r ds(on) vs. temperature figure 13. over load current vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 3.0 r ds(on) ( ) temperature ( c) 2.5 2.0 1.5 1.0 0.5 0 ? 40 ? 20 0 20 40 60 80 100 120 140 1.3 detection current (a) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 temperature ( c) output current ( a) output voltage (v) 13.5 14 14.5 15 15.5 16 16.5 17 17.5 18 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 temperature ( c) 1.0 leakage current ( a) ? 40 ? 20 0 20 40 60 80 100 120 140 t = 150 c i out = 600 ma outx = 13.5 v 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 open load detection current ( a) temperature ( c) ? 40 ? 20 0 20 40 60 80 100 120 140 100 90 80 70 60 50 40 30 20 10 0 outx = 13.5 v temperature ( c) threshold voltage 2.5 ? 40 ? 20 0 20 40 60 80 100 120 140 2.0 1.5 1.0 0.5 0 figure 14. output leakage vs. voltage (150 c) figure 15. output leakage vs. temperature figure 16. output load detection current vs. temperature figure 17. open load detection voltage vs. temperature i out = 100 ma
NCV7240 http://onsemi.com 11 typical performance graphs figure 18. output body diode voltage vs. temperature temperature ( c) body diode voltage 1.0 ? 40 ? 20 0 20 40 60 80 100 120 140 i out = ? 180 ma 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
NCV7240 http://onsemi.com 12 detailed operating description power outputs the NCV7240 provides eight independent 600ma power transistors with their source connection referenced to the ground pin and with their drain connection brought out to individual pins resulting in 8 independent low ? side drivers. output driver location on one side of the ic layout provides for optimum pcb layout to the loads. internal clamping structures are provided to limit transient voltages when switching inductive loads. each output has an over load detection current of 0.6 a (min) where the drivers turn ? off and stay latched off. an over load current shut ? down delay time of 3 s (min) is designed into the ic as a filter allowing for spikes in current which may occur during normal operation and allowing for protection from overload conditions. faults can be cleared with the spi input register (command 00) or via a power ? on ? reset. fault detection is provided in real time. detection is provided both during output turn ? on and with output already on. (see page 17, clearing the fault registers) the NCV7240 is available in a ssop ? 24 package. output control (spi) each output driver is controlled via a digital spi port after the device has powered up (out of por) and enabled via the en pin. the NCV7240 device will go through a power up reset each time the en pin is toggled high resulting in a device setup of default values as described in the register specifics section. standby mode, input mode, on mode, and off mode are all selectable via the spi for each channel independently. power up, power ? on reset (uvlo mode) both vdd and vdda supply an independent power ? on ? reset function to the ic. coming out of power ? on ? reset all input bits are set to a 1 (off mode) and all output bits are set to a 0 except for the ter bit which is set to a 1. the device cannot operate without both supplies above their respective power ? on reset thresholds with the exception of lhi mode. during lhi mode, vdd por is ignored and the device is only affected by vdda por. the NCV7240 powers up into the global off mode without the open circuit diagnostic current enabled. this allows the device to be turned on via en = 0 to en = 1 with led loads avoiding illumination of the led loads (reference figure 21 state diagram). all other paths to global off mode enable open circuit diagnostic current. table 1. modes of operation modes of operation conditions description uvlo mode vdd or vdda below their respective por thresholds all outputs off in this mode. coming out of this mode with en = 1 sets all channels in the off mode without open circuit diagnostic current enabled. with lhi = 1 and en = x, the part enters limp home mode. off mode spi control (command 11) output off. open circuit diagnostic current is disabled (powerup mode). open circuit diagnostic current is enabled (normal mode). global off mode spi control all channels (command 11) output off. open circuit diagnostic current is disabled (powerup mode). open circuit diagnostic current is enabled (normal mode). on mode spi control (command 10) output on. limp home mode (lhi) lhi = high, en = x dedicated output turn on control of out1 ? out4 using in1 ? in4. out5 ? out8 are in off mode. low iq mode en = lhi = low provides a state with the lowest quiescent current for v dd and vdda. standby mode spi control (command 00) provides an off state with open circuit diagnostic current disabled. global standby mode spi control all channels (command 00) provides a reduced quiescent current mode. provides an off state with open circuit diagnostic current disabled. input mode spi control (command 01) directs output channel to be driven from inx input pins.
NCV7240 http://onsemi.com 13 figure 19. basic state diagram figure 20. normal operation state diagram
NCV7240 http://onsemi.com 14 figure 21. detailed state diagram all channels off input reg = not accessible fault diag reg = not accessible all channels off open load diagnostics disabled spi commands ignored input reg = default= not accessible fault diag reg = default= not accessible in1 control to out1 in2 control to out2 in3 control to out3 in4 control to out4 out 5 ? 8 = off open load diagnostics enabled over load diagnostics enabled input spi commands ignored output spi faults reported input reg = not accessible fault diag reg = operational** input mode input data?01? stby mode input data?00? on mode input data?10? off mode input data?11? all channels off open load diag (powerup or out of lhi) disabled open load diag (normal) enabled input reg (normal) = defau lt=ffffh fault diag reg = default= 0000h ter = 1 (from uvlo, lhi, or low iq modes) all channels off open load diagnostics disabled input reg = default=0000h fault diag reg = default= 0000h uvlo_ mode lhi mode low_iq mode global_off_mode normal modes (per channel) open load diagnostic current enabled channel = off input pins muxed to outputs over load diagnostics enabled channel is on via spi control open load diagnostics disabled channel = off global_stby mode spi code = `0000h' * --- dotted line indicates bidirectional path. ** operational down to vdd=0 v. so reports above vdd > por open load diagnostic current enabled (if inx = 0) to uvlo mode to uvlo mode to uvlo mode to uvlo mode to uvlo mode lhi = ?1" en = ?x" lhi = en = ?0" lhi = ?1" lhi = ?1" lhi = en = ?0" en = ?0" en = ?0" * en = ?1" * spi codes per channel ?00", "01","10","11" spi code = ?0000h" spi code spi code spi code spi code spi codes per channel ?00", "01","10","11" spi code = `0000h' spi code = `1111h' (vdda NCV7240 http://onsemi.com 15 limp home and pwm operation (inx control) pulse width modulation techniques are allowed utilizing the parallel inputs (inx). output pins (outx) are programmed for use in conjunction with the inx pins using the spi command (command 01). the lhi pin controls the operation of the inx pins. lhi = low and en = high with lhi=low, default pairs of outputs are controlled by the inx pins (via spi programming). in1 controls channels out1 and out5. in2 controls channels out2 and out6. in3 controls channels out3 and out7. in4 controls channels out4 and out8. alternatively, any of the eight channels can be commanded off (e.g. if out5 is commanded off via a spi command, only out1 will be controlled via in1). output pins (outx) are programmed for use in conjunction with the inx pins using the spi command (command 01). it is important to note faults occurring during pwm operation (lhi = low) must be cleared via the spi port. lhi = high to go into limp home mode, bring lhi=high, the corresponding outputs of in1 ? in4 will turn on or off, and out5 ? out8 will be forced off. during limp home mode, over load and over temperature sensing are functional, and are reported via the spi port. but, since input spi commands are ignored with lhi = high, driver turn ? off (overload or over temperature) occurring when lhi=high can only be re ? initiated by toggling lhi or through a por of vdda. all registers are reset coming out of lhi mode. the device enters off mode (en = 1) or low iq mode (en = 0) depending on the state of the en pin. open load diagnostics are disabled in both cases. uvlo (under voltage lockout with lhi = high) a breach of vdda power ? on reset thresholds will cause the outputs to turn off and enter the uvlo mode. in lhi mode (lhi = 1), vdd por is ignored. if vdd is below the operation of so drive capability, fault information is preserved and can be retrieved when so drive capability is restored. ter a transmission error bit (ter) is set (?1?) when exiting the limp home mode into global off mode. see frame detection transmission error section for operation details. enable input (en) the en input pin is a logic controlled input with a voltage threshold between 0.8 v and 2.0 v. the device powers up when en goes from low to high, and exits low iq mode (with lhi = 0 v) into global off mode. device power up is also controlled via the limp home input (lhi) as an or?d condition. the en input is a don?t care when the lhi pin is driven from low to high. in this situation, the device enters limp home mode. output drive clamping internal zener diodes (z1 & z2, figure 22) help to protect the output drive transistors from the expected fly back energy generated from an inductive load turning off. z1 provides the voltage setting of the clamp (along with v gs of the output transistor and z2) while z2 isolates z1 from normal turn ? on activity. the output clamp voltage is specified between 36 v and 44 v. this includes clamping operation during unpowered input supplies (vdd and vdda). device protection will be provided when the load is driven from an alternative driver source. this is an important feature when considering protecting for load dump with an un ? powered ic.
NCV7240 http://onsemi.com 16 vdrain = vz 1 + vz 2 + vgs z1 z2 g s drain vbat gnd vdd vdda outx v bat v clamp = 36v (min) to 44v (max) powered gnd vdd vdda outx v bat alternative driver source v clamp = 36v (min) to 44v (max) un- powered figure 22. output clamp over temperature / thermal shutdown the NCV7240 incorporates eight individual thermal sensors located in proximity to each output driver. a channel is latched off upon the detection of an over temperature event. this allows operation of unaffected channels before, during, and after a channel detection of over temperature. the thermal shutdown detection threshold is typically 175 c with 25 c of hysteresis. open load detection open load detection is achieved for each output with the open load detection threshold voltage reference voltage (vol) and its? corresponding open load diagnostic sink current (when the output driver (outx) is off). the output driver maintains its? functionality with and without the open bit set (i.e. it can turn on and off). during normal operation, the open circuit impedance (roc) is 0 . this sets the voltage on outx to v bat volts. as long as v bat is above v ol no open circuit fault will be recognized. the voltage appearing on outx is a result of v bat and the voltage drop across roc realized by the current flow created by iol. the NCV7240 voltage level trip points are referenced to ground. the threshold range is between 1.0 v and 2.5 v. with a nominal battery voltage (v bat ) of 14 v, the resultant worst case thresholds of detection are as follows. v bat openloaddetectionthresholdvoltage openloaddiagnosticsinkcurrent openload impedance 14 v 2.5 v 100 a 115 k 14 v 1.0 v 20 a 650 k
NCV7240 http://onsemi.com 17 + ? open load detection channel x gnd outx open load flag 1.75v roc 60ua output turn ? on control vol iol vol = open load detection threshold voltage iol = open load diagnostic sink current open load detection is active when the driver is off, in lhi mode, or off mode ( command 11 ). figure 23. open load detection v bat note: detection of an open load condition is limited by the parallel control output turn ? off time and the open load detection time specifications. the maximum allowable frequency of operation for pwm (pulse width modulation) using the inx inputs is calculated from the maximum limits of these specifications. inx must be low for longer than the sum of these maximum specifications (50 sec and 200 sec). assuming a 50% duty cycle yields a maximum frequency of operation of [1/(2*(50 + 200 ))]=2 khz. led loads the NCV7240 features a power up feature for the global off mode enabling the part to power up in a mode without the open load diagnostic current enabled. this averts any unintended illumination of led loads during power up. programming features the NCV7240 provides two registers. 1. input register. input for ic mode state and output driver state control. 2. output register. provides diagnostic information on the output driver condition. clearing the fault registers registers are reset with the following conditions. 1. channel in standby mode. 2. power ? on reset of vdd. 3. power ? on reset of vdda. 4. en low. 5. coming out of limp home mode(lhi). spi ? interface the device provides a 16 bit spi ? interface for output drive control and fault reporting. data is imported into the NCV7240 through the si (serial input) pin. data is exported out of the NCV7240 through the so (serial output) pin. the input ? frame (si) (2 bits / channel) is used to command the output stages. the response frame (so) provides channel ? specific (2 bits / channel) status information fault reporting. words should be composed of 16 bits msb (most significant bit) transmitted first.
NCV7240 http://onsemi.com 18 frame detection transmission error (ter) the NCV7240 detects the number of bits transmitted after csb goes low. bit counts not a multiple of 8 (16 bit minimum) are reported as a fault on the ter bit. the transmission error information (ter) is available on so after csb goes low until the first rising sclk edge. reference the serial peripheral interface diagram (figure 27). in addition to unqualified bit counts setting ter = 1, the bit will also be set by 1. coming out of uvlo. 2. transitioning from limp home mode to global off mode. 3. transitioning from low iq mode to global off mode. the ter bit is cleared by sending a valid spi command. the ter bit is multiplexed with the spi so data and or?d with the si input (figure 24) to allow for reporting in a serial daisy chain configuration. a ter error bit as a ?1? automatically propagates through the serial daisy chain circuitry from the so output of one device to the si input of the next. this is shown in figures 25 and 26 first as the daisy chained devices connected with no t ransmission error (figure 25) and subsequently with a transmission error in device 1 propagating through to device 2 (figure 26). si ter spi si so s so si ter so NCV7240 si ter so NCV7240 ?0? ?0? ?0? ?0? ?0? device #1 device #2 figure 24. ter spi link figure 25. ter (no error) si ter so NCV7240 si ter so NCV7240 ?0? ?1? ?1? ?0? ?1? device #1 device #2 figure 26. ter error propagation note: ter is valid from csb going low until the 1 st low ? to ? high transition of sclk to allow for propagation of the si signal. reference figure 27. for proper ter status retrieval, si should be in a low state.
NCV7240 http://onsemi.com 19 ter information retrieval ter information retrieval is as simple as bringing csb high ? to ? low. no clock signals are required. b9 b10 b11 b12 b13 b14 b15 b7 csb si sclk so msb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 lsb b0 b1 b2 b3 b4 b5 b6 b0 b8 ter figure 27. serial peripheral interface the timing diagram highlighted in figure 27 shows the spi interface communication. note: 1. the msb (most significant bit) is the first transmitted bit. 2. data is sampled from si on the falling edge of sclk 3. data is shifted out from so on the rising edge of sclk 4. sclk should be in a low state when csb makes a transition. frame detection input word integrity (si) is evaluated by the use of a frame consistency check. the word frame length is compared to an n * 8 bit (where n is an integer) acceptable word length (16 ? bit minimum) before the data is latched into the input register. this guarantees the proper word length has been imported and allows for daisy chain operation applications with 8 ? bit spi devices. the frame length detector is enabled with the csb falling edge and the sclk rising edge. reference the valid spi frame shown below. (figure 27) csb si sclk b7 b6 b5 b4 b3 b2 b1 b0 frame detection starts after the csb falling edge and the sclk rising edge . internal counter 9 10 11 12 13 14 15 16 frame detection mode ends with csb rising edge . valid 16 bits shown 12 345678 b15 b14 b13 b12 b11 b10 b9 b8 figure 28. frame detection daisy chain setup
NCV7240 http://onsemi.com 20 serial connection daisy chain setups are possible with the NCV7240. the serial setup shown in figure 29 highlights the NCV7240 along with any 16 bit device using a similar spi protocol. particular attention should be focused on the fact that the first 16 bits which are clocked out of the so pin when the csb pin transitions from a high to a low will be the diagnostic output data from the fault output register. these are the bits representing the status of the ic. additional programming bits should be clocked in which follow the diagnostic output bits. the timing diagram shows a typical transfer of data from the microprocessor to the spi connected ic?s. ic4 NCV7240 csb sclk si so ic3 csb sclk si so ic2 csb sclk si so any ic using 16 bit spi protocol csb sclk si so microprocessor ic1 any ic using 16 bit spi protocol any ic using 16 bit spi protocol figure 29. serial daisy chain { { { { csb sclk si 1 st cmd 2nd cmd 3rd cmd 4th cmd figure 30. serial daisy chain timing diagram table 2. serial daisy chain data pattern clk = 16 bits clk = 32 bits clk = 48 bits clk = 64 bits ic4 1st cmd 2nd cmd 3rd cmd 4th cmd ic3 ic4 diag 1st cmd 2nd cmd 3rd cmd ic2 ic3 diag ic4 diag 1st cmd 2nd cmd ic1 ic2 diag ic3 diag ic4 diag 1st cmd micro ic1 diag ic2 diag ic3 diag ic4 diag table 2 refers to the transition of data over time of the serial daisy chain setup of figure 29 as word bits are shifted through the system. 64 bits are needed for complete transport of data in the example system. each column of the table displays the stat us after transmittal of each word (in 16 bit increments) and the location of each word packet along the way.
NCV7240 http://onsemi.com 21 8 ? bit devices the NCV7240 is also compatible with 8 bit devices due to the features of the frame detection circuitry. the internal bit counter of the NCV7240 starts counting clock pulses when csb goes low. the 1st valid word consists of 16 bits and each subsequent word must be comprised of just 8 ? bits (reference the frame detection section). ic2 NCV7240 csb sclk si so ic1 csb sclk si so microprocessor any ic using 8 bit spi protocol the NCV7240 is also compatible with 8 ? bit devices compatibility note the sclk timing requirements of the NCV7240. data is sampled from si on the falling edge of sclk. data is shifted out of so on the rising edge of sclk. devices with similar characteristics are required for operation in a daisy chain setup. figure 31. serial daisy chain with 8 ? bit devices parallel connection a more efficient way (time focused) to control multiple spi compatible devices is to connect them in a parallel fashion and allow each device to be controlled in a multiplex mode. figure 32 shows a typical connection between the microprocessor or microcontroller and multiple spi compatible devices. in a serial daisy chain configuration, the programming information for the last device in the serial string must first pass through all the previous devices. the parallel control setup eliminates th at requirement, but at the cost of additional control pins from the microprocessor for each individual csb (chip select bar) pin for each controllable device. serial data is only recognized by the device that is activated through its? respective csb pin. figure 33 shows the waveforms for typical operation when addressing ic1. csb3 sclk si csb2 csb1 NCV7240 csb sclk si so microprocessor out1 out2 out3 NCV7240 csb sclk si so out1 out2 out3 NCV7240 csb sclk si so out1 out2 out3 csb chip1 csb chip2 csb chip3 si sclk so ic1 ic2 ic3 figure 32. parallel connection figure 33. parallel connection timing diagram
NCV7240 http://onsemi.com 22 stepper motor operation the NCV7240 device is capable of driving stepper motors. each stepper motor requires 4 low ? side drive outputs. consequently, each NCV7240 device is capable of driving two stepper motors. figure 34 below illustrates a unipolar stepper motor setup . for proper operation, the code listed in t able 3 should be used (and repeated) for one way operation (clockwise). for reverse direction, simply reverse the code and repeat (counterclockwise). outputs 1 ? 4 are utilized for one stepper usage. for a 2 nd stepper motor, repeat the code used for outputs 1 ? 4 to outputs 5 ? 8. during operation waveforms similar to figure 35 can be expected on the outx pins. figure 34. stepper motor operation setup out4 out3 out2 out1 NCV7240 stepper motor figure 35. typical stepper motor waveform (unipolar portescap 35l048l32u) v bat v bat = 12 v table 3. NCV7240 stepper motor code out 4 out 3 out 2 out 1 off on off on on off off on on off on off off on on off {repeat}
NCV7240 http://onsemi.com 23 input register (via spi) output on / off control output register (via so) open load / (over load or over temperature) fault output register spi csb sclk si so 00=stand ? by mode 01=input mode 10=on mode 11=off mode transmission error bit ? only valid from csb going low to sclk going high. command figure 36. spi register overview figure 36 displays the functions controlled and reported via the spi port. the input register controls the input source (parallel or spi) and the spi input data. the output register transmits the output fault bits and the frame detection integrity.
NCV7240 http://onsemi.com 24 si spi inp ut data (16-bit serial structure of input word) the 16 ? bit data received (si) is decoded into instructions for each channel per the table below. after a power ? on reset, all register bits are set to a 1. table 4. spi input data channel 8 channel 7 channel 6 channel 5 channel 4 channel 3 channel 2 channel 1 msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 input data register field bits description channel x (x = 1 ? 8) 15, 14 13, 12 11, 10 9, 8 7, 6 5, 4 3, 2 1, 0 command 00 channel stand ? by mode fast channel turn off fault registers reset diagnostic current disabled 01 input mode channel input directed to inx. (reference pwm operation section). diagnostic current enabled in off state. 10 on mode channel turned on. diagnostic current disabled 11 off mode channel turned off. diagnostic current enabled (disabled after por)* *for proper led load operation. so (fault diagnostic retrieval) output fault diagnostics from the output fault diagnostic register are shifted out on any 16 bit word clocked into serial input (si). only output fault diagnostics and frame detection errors are available through the serial output (so). table 5. spi output data ter ol8 d8 ol7 d7 ol6 d6 ol5 d5 ol4 d4 ol3 d3 ol2 d2 ol1 d1 fault diagnostic register field bits description ter csb high ? to ? low prior to 1st sclk low ? to ? high transmission error. 0 successful transmission in previous communication. 1 frame detection error in previous transmission or exiting limp home mode or exiting uvlo mode. oln (n = 1 ? 8) 1, 3, 5, 7, 9, 11, 13, 15 open load 0 normal operation 1 fault detected dn (n = 1 ? 8) 0, 2, 4, 6, 8, 10, 12, 14 over load or over temperature 0 normal operation 1 fault detected
NCV7240 http://onsemi.com 25 table 6. fault conditions output fault condition fault memory miscellaneous open load latched detected in driver off state (1.75 v [typ] threshold) when detection is enabled. reported in output fault diagnostics register until cleared via the spi port. output will maintain turn ? on capability. short to ground latched detected as part of the open load circuitry described above. short to v bat n/a protected via over load and over temperature functions. over load latched detected in driver on state 0.6 a [min], 1.3 a [max]. a latched off condition must be cleared via the spi port before it can be turned on. over temperature latched detected in ic on state (t j = 175 c [typ]) a latched off condition must be cleared via the spi port before it can be turned on. device ordering information part number package type shipping ? NCV7240dpr2g ssop ? 24 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCV7240 http://onsemi.com 26 package dimensions case 565al issue o dim min max millimeters a 1.75 a1 0.10 0.25 l 0.40 1.27 e 0.65 bsc c 0.19 0.25 h 0.22 0.50 b 0.20 0.30 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension e1 does not inlcude inter- lead flash or protrusion. interlead flash or protrusion shall not ex- ceed 0.15 per side. d and e1 are de- termined at datum h. 5. datums a and b are determined at datum h. pin 1 reference d e1 0.10 seating plane 24x b e e detail a 1.35 soldering footprint* l l2 gauge detail a e1 3.90 bsc plane seating plane c c h end view a-b m 0.25 d c top view side view d 0.20 c 112 24 a b d 2x 12 tips a1 a2 c c 24x d 8.65 bsc e 6.00 bsc 24x 1.12 24x 0.42 0.65 dimensions: millimeters pitch 6.40 1 2x a h x 45 12 24 13 m 13 d 0.25 c d 0.20 c 2x 0.10 c recommended a2 1.50 1.25 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCV7240/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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